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 Post subject: Let's do something constructive about the MyIDE+F stability.
PostPosted: Wed Apr 13, 2011 6:33 pm 
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Location: Cleveland, Ohio
There are quite a few non SECAM users having the same problem with MyIDE+Flash stability.

At least the IDE part, I don't see any complaints about the flash cartridge part of the interface.

The fix for MyIDE and SECAM will very likely fix most of these issues, but I can't start recommending people send back interfaces in bulk to apply the changes to Sijmen's design unless its shown to actually work.

I don't have any Atari computers with this issue except a SECAM 800XL, so I need your help to test it.

If you have a setup where you just can't get your MyIDE+Flash to work, or you have a really hard time finding devices that work, please post here or e-mail me to arrange an exchange of your interface for one that has the fix pre-applied. :P

I'm sure your help in actually finding and erasing the problem will be appreciated by everyone also effected by this issue.

If you want to post or e-mail details about your setup, even better. If there is a pattern to be found I'm sure more eyes are better, so to speak.

Thanks,

Steve


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 Post subject: Re: Let's do something constructive about the MyIDE+F stabil
PostPosted: Thu Apr 14, 2011 1:52 am 

Joined: Wed Mar 04, 2009 7:27 am
Posts: 98
Location: United Kingdom
If you post the details, it's something I'd like to implement myself and test out.



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 Post subject: Re: Let's do something constructive about the MyIDE+F stabil
PostPosted: Thu Apr 14, 2011 4:49 am 

Joined: Mon Dec 20, 2010 9:10 am
Posts: 31
Location: Sheffield, England - U.K.
It would be helpful if we could also identify the ataris with timing issues, so that we could avoid wasting time installing MyIDE. To date there's no definitive answer.


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 Post subject: Re: Let's do something constructive about the MyIDE+F stabil
PostPosted: Thu Apr 14, 2011 5:53 am 

Joined: Wed Mar 04, 2009 7:27 am
Posts: 98
Location: United Kingdom
I doubt there ever will be a definitive answer. What's required is an interface which copes with the variance in the Atari's timing. The design of the computer is fundamentally sound, and it's often an accumulation of bus capacitance caused by various mods and upgrades which causes the problems. Of course, there are situations where a computer's stock timing is off. But you don't want to be in a situation where everyone who buys the MyIDE also has to lift the lid and start doing timing mods to tune the computer to the interface. This can often mean - with the addition of a memory upgrade and some other internal stuff - that when you plug some other IDE interface into the parallel bus, the timing's off for that one. The firmware ("BIOS") for the MyIDE has hitherto been designed with quite breathtakingly exhaustive error correction, which has absolutely crippled performance when compared to most interfaces which follow the PBI/ECI standard (i.e. those which load their firmware into the PBI ROM space in the Atari's OS). There's nothing wrong with a cartridge device which uses a soft-OS or driver per se, but it should WORK, regardless of how inexpensive it is. Many users who have experienced stable operation using Sijmen's I/O routines MAY be seeing a simulation of stable operation, as the driver works double time to re-read and re-send sectors corrupted through dropped bytes which have failed the verification check. Getting 64KB/s and more out of this interface isn't rocket-science; a good programmer with a sound understanding of the IDE protocols should be able to write a fast driver (such as the SDX driver). However, if the author then finds that half his potential users have interfaces which in fact never operated stably in the first place (they only appeared to when running under the driver with exhaustive error correction), one is inclined to give up altogether and go find a device which is stable.

I like the MyIDE interface. It's cheap, portable, and was great fun to develop for. If Steve can come up with a good fix on the interface side of things, that's a positive move.



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 Post subject: Re: Let's do something constructive about the MyIDE+F stabil
PostPosted: Thu Apr 14, 2011 7:08 am 
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Location: netherlands
You are spot on.

MyIDE was never intended to be a flawless interface, so that's why it is as it is.
It's cheap and works quit nicely. That is to my opinion that counts.
Nobody benefids from a non working device.

Later,
Sijmen.


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 Post subject: Re: Let's do something constructive about the MyIDE+F stabil
PostPosted: Thu Apr 14, 2011 7:39 am 

Joined: Mon Jun 21, 2004 7:53 am
Posts: 325
It may not be a 100% fix, but I've had several computers (typically with expanded memory mods) that give my various HD's errors (that means PBI devices as well as MyIDE). The fix that always has worked for me on my NTSC computers is fix #1 from Bob Puff. It is generally a very simple fix (two solder connections, but still assumes that the user knows his way around a soldering iron). The fixes are posted under "Miscellaneous" at:

http://www.nleaudio.com/css/Files.htm

The other offending group seems to be eprom's and OS modules used in place of the stock rom OS. Puff's fix #2 seems to always correct that for me. Sometimes just swapping the eprom for a different mfg./speed seems to work fine, but that has been more trial-and-error. Fix #2 is quite a bit more complicated in the 130XE; not so bad in the 800XL. If you have an OS module then be very careful about how you would apply #2, since the it is extremely easy to break pins off the module, and then you DO have a problem.

A case in point -- Mr-Atari's new 4.6 Beta in a flash cartridge worked great in an 800-XL (which already had fix #1 and #2 applied) but it would not even boot in a dead stock 130XE. I applied fix #1 and it worked with zero errors.

BTW, Drac030 has posted a new utility that can help you determine your HD system integrity. Check out RW-CRC:

http://drac030.krap.pl/en-inne-pliki.php

-Larry


Last edited by thewhiz on Thu Apr 14, 2011 8:29 am, edited 1 time in total.

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 Post subject: Re: Let's do something constructive about the MyIDE+F stabil
PostPosted: Thu Apr 14, 2011 8:01 am 

Joined: Mon Jan 23, 2006 10:49 am
Posts: 187
Location: Salzburg, Austria
Hi Steve!
classics wrote:
The fix for MyIDE and SECAM will very likely fix most of these issues, but I can't start recommending people send back interfaces in bulk to apply the changes to Sijmen's design unless its shown to actually work.

What does this fix actually do? It would be great if you could post (or email) some details about it, so we could try it without shipping the cart around.

I haven't used the cart for quite a while, instead I'm using an internal interface I built by myself (using a GAL 22V10 and a 74LS245). I guess most of the issues also apply to the flash cart.

One of the main problems with Ataris is the damned PHI2 signal. Problem here is the falling edge being slightly too late, reducing the slack time (until R/W and Ax change) to 0-40ns - normally one would expect at least 30ns minimum. The exact values vary across Ataris, I checked several computers with my scope.

To prevent false writes I simply used PHI0 for generating the IOW signal on my internal interface. This fix is not easily applicable to the cart of course, so I can't help here...

But there are other issues:

The original cart by Sijmen had the address lines on the IDE bus connected directly to the Atari's address lines - which is a bad idea (not sure if this is also the case with the flash cart). A buffer on these lines is absolutely needed, actually all signals going to the IDE bus have to be buffered. In my interface I just run these signals through the GAL, which also compensates (part of) the skew introduced by address decoding logic on the IOR/IOW and CS lines.

With this setup my two Sandisk CF cards worked like a charm, but I still got some occasional errors on my 4GB Kingston CF card ("133x elite pro"). This puzzled me for quite some time, and I couldn't find an explanation why it failed (according to my logic analyzer captures everything seemed to be fine). A few weeks ago I looked at this issue again and checked the signals on the IDE bus with my scope:

On the IOR, IOW and CS lines I saw slight ringing (over/undershoot) at the signal edges. This is not good, but could be fixed quite easily by adding a 33 ohm series resistor (acting as source termination) in these lines. Now even the 4GB Kingston card worked 100% stable!

I checked the ATA parallel transport docs, especially chapter 4 and annex B. It mentions that for UDMA several series termination resistors are required, at the host and at the device (page 18). Well, the MyIDE interface isn't actually doing UDMA, but it seems like various UDMA capable devices, like my Kingston CF card, act weird even when operating in PIO mode. I guess this card would also have problems if I connected it to some old PIO-only IDE controller on a 386 or so.

So far I haven't added the series resistors to the address and data lines, and exchanging the 74LS245 for a 74HCT245 results in data corruption. Again, this could be due to ringing/crosstalk/whatever. I haven't yet had the time to do more tests, but I guess adding the resistors might be a good idea.

So, bottom line is: have buffers on all signals and series termination as described in the ATA docs.

so long,

Hias

BTW: here's the GAL logic source, in case you are interested. "ENIDE" connects to the D1xx select line of the LS138, "TREN" connects both to the LS245 "transceiver enable" input and the IDE CS line.
;PALASM Design Description

;---------------------------------- Declaration Segment ------------
TITLE    MyIDE
PATTERN
REVISION 1.0
AUTHOR   Matthias Reichl
COMPANY  HiassofT
DATE     2010/09/21

CHIP  myide22  PALCE22V10

;SIGNATURE HIAS

;---------------------------------- PIN Declarations ---------------
PIN 1           PHI2    COMBINATORIAL   ; INPUT
PIN 2           PHI0    COMBINATORIAL   ; INPUT
PIN 3           RW      COMBINATORIAL   ; INPUT
PIN 4..11       A[0..7] COMBINATORIAL   ; INPUT
;PIN 12         GND

PIN 13          /ENIDE  COMBINATORIAL   ; INPUT
PIN 14          TRDIR   COMBINATORIAL   ; OUTPUT
PIN 15          /TREN   COMBINATORIAL   ; OUTPUT
PIN 16..18      ADR[0..2]
PIN 19          /IOR    COMBINATORIAL   ; OUTPUT
PIN 20          /IOW    COMBINATORIAL   ; OUTPUT
;PIN 24         VCC

STRING IDESEL '(ENIDE * /A[4] * /A[5] * /A[6] * /A[7])'

;----------------------------------- Boolean Equation Segment ------
EQUATIONS

; transceiver direction
TRDIR = /RW

; transceiver enable
TREN = IDESEL

; IDE access
IOR  =  RW * PHI2 * IDESEL
IOW  = /RW * PHI0 * IDESEL

; address output
ADR[0] =   IDESEL * A[0]
ADR[1] =   IDESEL * A[1]
ADR[2] =   IDESEL * A[2]


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 Post subject: Re: Let's do something constructive about the MyIDE+F stabil
PostPosted: Thu Apr 14, 2011 8:23 am 

Joined: Wed Mar 04, 2009 7:27 am
Posts: 98
Location: United Kingdom
thewhiz wrote:
BTW, Drac030 has posted a new utility that can help you determine your HD system integrity. Check out RW-CRC:

http://drac030.krap.pl/en-inne-pliki.php

Thanks Larry: almost missed that one. :)



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 Post subject: Re: Let's do something constructive about the MyIDE+F stabil
PostPosted: Thu Apr 14, 2011 10:37 am 

Joined: Mon Dec 20, 2010 9:10 am
Posts: 31
Location: Sheffield, England - U.K.
Q. Does the phi2 problem occur on machines with/without FREDDIE chip?

Q2. Could the 6502C be the problem (ie NCR vs. Mexico)?

My 65XE has a couple of wires added:
a) '138 pin-8 to another cap in series+smoothing cap between ANTIC & GTIA.
b) '08 pin-9 to '138 pin-15

is this an engineering change at the factory? iow is it common?


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 Post subject: Re: Let's do something constructive about the MyIDE+F stabil
PostPosted: Thu Apr 14, 2011 1:24 pm 

Joined: Mon Jan 23, 2006 10:49 am
Posts: 187
Location: Salzburg, Austria
STA_wsync wrote:
Q. Does the phi2 problem occur on machines with/without FREDDIE chip?

From my experience this doesn't make a difference, the problems occur on all kinds of machines.

Quote:
Q2. Could the 6502C be the problem (ie NCR vs. Mexico)?

Yes, bad CPUs can be an issue and replacing them might help. Although many people reported that they had troubles with Mexico CPUs it doesn't mean all Mexico CPUs are bad (or that other CPUs are better). For example I had one 800XL with a non-Mexico CPU (can't remember which manufacturer) and replacing it with a Mexico CPU helped a lot.

Also keep in mind that there are other factors as well (the rest of the system hanging on the bus), and adding upgrades to the Atari might make things worse.

Quote:
My 65XE has a couple of wires added:
a) '138 pin-8 to another cap in series+smoothing cap between ANTIC & GTIA.
b) '08 pin-9 to '138 pin-15

In my PAL 130XE (REV-B board) I have a wire from '138 pin 15 (this is the $D0xx output, usually going to GTIA chip select on 800XLs) to pins 9 and 10 of the '08, and pin 8 from the '08 going to GTIA pin 32 (chip select). On the bottom of the board the trace originally going from the '138 to the GTIA is cut - so Atari seems to have "fixed" some timing issues.

so long,

Hias


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 Post subject: Re: Let's do something constructive about the MyIDE+F stabil
PostPosted: Thu Apr 14, 2011 2:28 pm 
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I'll post pictures and instructions to DIY the fix when I get home tonight.

You will need a 74LS574 or a GAL16V8 to latch A0..A2 past the end of phi2. Some traces near the IDE connector need to be cut, and some wires soldered.

I don't actually have any LS574 on hand so I've been using the GAL, but it should work the same.

Steve


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 Post subject: Re: Let's do something constructive about the MyIDE+F stabil
PostPosted: Fri Apr 15, 2011 6:06 am 

Joined: Mon Jan 23, 2006 10:49 am
Posts: 187
Location: Salzburg, Austria
Hi Steve,

thanks a lot for posting the instructions!

A few remarks on this:

The GAL/'574 isn't actually a latch, but a register (D-type flip flop). This means the outputs change state on the rising edge of PHI2.

This still isn't 100% perfect, as the IDE standard requires A0-A2 and CS0/1 to be valid some 25-70ns before IOR/IOW are asserted ("t1" parameter on page 137/138). Since IOR/IOW are gated with PHI2, and I assume the propagation delays of the additional 16V8 GAL and the 26V12 on the card to be similar, the signals change state at approx. the same time (i.e. t1=0ns). I can't tell how devices react on this, haven't tested it yet. But of course Ax changing before/at the falling edge of PHI2 is fixed.

A proper solution is somewhat tricky, but certainly doable. What we want is Ax (and CS0) to pass through to the IDE bus some time (at least 70ns) before the rising edge of PHI2 and then keep their state some time (at least 20ns + tPd of the 26V12) after the falling edge of PHI2. The address lines on the 6502 are ususally valid quite early, so we just need to concentrate on latching the state past the end of PHI2.

We don't have a signal readily available that extends past PHI2, but we can create on by our own, using a single-shot/monoflop (like the 74LS123), triggered at the rising edge of PHI2 and configured to a pulse-width of approx. 300-350ns. This creates a signal that goes high some 20-30ns after the rising edge of PHI2 (tPLH) and then goes low again 300-350ns later - that's some 40-100ns after the trailing edge of PHI2 (note: in other projects I used the '123 to shorten write pulses, but this time we create a signal longer than PHI2 to latch the signals).

We can then use this signal to control a latch, for example a LS373. The '373 latches a signal at the falling edge of it's clock input (and thus holds the value during C=0) and lets it pass through during C=1, so we need an inverted version of our previously created signal. Fortunately, this is no problem, the '123 also has an inverted output, so we just use this.

BTW: it's best to run both the address lines and also the R/W line through this latch, and only use the latched lines for everything on the cart - so cut the lines directly at the cartridge port and put the latch there, so that the GALs also use the latched signals.

So, what does this circuit actually do?

Some 40-100ns after the beginning of each cycle (the falling edge of PHI2), it begins passing Ax and R/W from the Atari through to the cart. At ~280ns PHI2 goes high, some 20ns later the clock input of the latch goes low and the signals are "frozen". Then at ~560ns PHI2 goes low, IOR/IOW are deasserted (with a tPd delay of the GAL), then some 40-100ns later the latch gets decativated and signals are passed through again. I guess this could work :-)

so long,

Hias


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 Post subject: Re: Let's do something constructive about the MyIDE+F stabil
PostPosted: Fri Apr 15, 2011 6:58 am 
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Hi Hias,

Thanks for your analysis. Here is a graph of the write cycle timing with the fix applied. I made this some time ago, maybe a year but I'm pretty sure it was from the SECAM fixed cartridge. Maybe it will help clarify what is actually happening, but you seem to have it right already.

I see what you are taking about with the setup time for A0..A2, it will be interesting to see if that is actually an issue with any devices.

I suppose it depends on how the device handles reads and writes internally, which is not ideal.

If writes are latched on the rising edge of IOW and read fifos are decremented on the rising edge of IOR, then it should work, as the target register address will always be valid at that time.

I think the only thing not shown here is that IOR is latched internally by the 26v12 once asserted, until the end of /CCTRL.

Since there is a large amount of time between /CS0 and IOR/IOW, adding a RC delay to the LE pin on the LS573 might be fine to keep it held stable for some ns after o2. The delay at the beginning of the cycle won't effect anything.

Steve


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 Post subject: Re: Let's do something constructive about the MyIDE+F stabil
PostPosted: Fri Apr 15, 2011 7:07 am 

Joined: Thu Feb 05, 2004 10:34 am
Posts: 259
Location: NL
I have written in the past about my very well working fix, and no-one ever took the time to explain why my fix works. Here it comes again. I'm REALLY interested in the reason WHY it works, but I'm rather sure it is interesting to think about.

My fix is this:

1. I connect the MyIDE cartridge as usual
2. I connect a IDE -> CF adapter to the MyIDE interface
3. The IDE->CF adapter is powered by the MyIDE interface, so the power connector of the IDE->CF adapter is not used
4. I solder 2 small (rather thick) wires to the center pins of the power connector of the IDE->CF adapter *
5. Those two wires are connected to a audio cinch connector (both mass and center pin)
6. I connect this to the RF-Out (!) of the atari computer

*) longer wire does fail, and thin wire too.


And there I go: my MyIDE works. Works here on any computer that failed before. It's true, and no joke.

Also computers with the RF shield installed has a better chance. The more mass (ground) the better it works.

The only thing I want to know is: WHY does my trick work. What is it, that this does the trick. It's definately the easiest fix in the world.

Thanks
Marius


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 Post subject: Re: Let's do something constructive about the MyIDE+F stabil
PostPosted: Fri Apr 15, 2011 7:45 am 
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Hi Marius,

Is that one of the older MyIDE? Does it have any bypass capacitors and bulk capacitors inside?

Good bypassing, bulk capacitors close to the power source to the CF adapter and good grounds may replicate what you are seeing with the phono plug.

'Magic' fixes like this often work due to problems with noise, poor grounds or other power supply issues.

Steve


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