;probably incorrect comments written by Jindroush (kubecj@asw.cz)

chip rambox2 GAL20V8

i_nc0=1
i_cctl=2
i_rw=3
i_b01=4
i_res=5
i_b02=6
i_ld7=7
i_b04=8
i_b05=9
i_phi2=10
i_la16=11
GND=12 
!nc13=13
i_la17=14
o_rom_oe=15
o_clkd=16
o_clka=17
o_ras=18
o_cas=19
o_ma8=20
o_rd5=21 
o_rd5n=22
i_a7=23
VCC=24 

@ues ffffffffffffffff
@ptd unused

equations

;rd5n will be low if D7 is low & RD5 is high
o_rd5n = i_ld7 # !o_rd5
o_rd5n.oe = vcc

;RD5 will be high if rd5n is low or res is low (when pressed)
o_rd5 = !i_res # !o_rd5n
o_rd5.oe = vcc

;multiplicated 2 upper bits of address
o_ma8 = !i_b01 & i_la17 # i_b01 & i_la16
o_ma8.oe = vcc

;cas is generated if 
;first line - write accessing D580-D5FF
;second line - read accessing D580-D5FF
;third line - ?
!o_cas = !i_cctl & i_a7 & !i_rw & i_b02 & !i_b05
    # !i_cctl & i_a7 & i_rw & i_b02 & i_phi2
    # !i_b01 & i_b05
o_cas.oe = vcc

o_ras = i_cctl & i_b02
    # i_cctl & !i_b05
    # i_b02 & !i_phi2
    # !i_b05 & !i_phi2
o_ras.oe = vcc

;clocks when write accessing D500-D57F. Goes to RAM bank register (7bits). B04 & B05
;states unknown to me.
o_clka = !i_cctl & !i_a7 & !i_rw & !i_b04 & i_b05
o_clka.oe = vcc

;clocks only when write accessing D500-D57F. Goes to ROM 74LS273 8bit
;register (3bits). Hi 4 bits of bank register.
o_clkd = i_cctl # i_rw # !i_phi2 # i_a7
o_clkd.oe = vcc

;puzzling - should be low to select rom, but will be oscillating if reading &
RD5 high. If writing or RD5 low, there will be constant high state on OE.
o_rom_oe = !i_rw # !i_phi2 # !o_rd5
o_rom_oe.oe = vcc