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Article #38 (51 is last):
From: aa700@cleveland.Freenet.Edu (Michael Current)
Newsgroups: freenet.sci.comp.atari.product.8bit.tricks
Subject: The Turbo Atari 8-bit
Reply-To: aa700@cleveland.Freenet.Edu (Michael Current)
Posted-By: xx004 (aa700 - Michael Current)
Date: Tue Jun  1 21:21:22 1993




 From: theclub!conklin@egr.msu.edu (Terence Conklin)

Copyright 1993 Terence Conklin.  Reprinted with permission.

-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-

A popular dream amongst Atari 8-bitters is the idea of a speed-up mod. The 
purpose of a speed-up mod is, quite simply, to increase the CPU clock rate
and thus boost performance.  IBM compatibles are commonly identified by MHZ,
with given machines like a 386 available at 20 or 40 Mhz. IBM compatibles,
and TRS-80s before them, get a more or less linear speed increase.
I.E. double the clock is twice speed.  A powerful punch for an Atari which 
already sports co-processors.

Designing the turbo mod, however, involves a number of hurdles. In fact,
it's akin to an Olympic Grand Prix, where the horses face impossibly high
obstacles and even one mistake means failure.  Here are the obstacles we found,
and the answers to them, in the order they were encountered:

High speed 6502 processors

On the Atari, until a few years back, 6502 processors were not available
in higher speeds. The Atari 6502, running at 1.7+ Mhz, is actually pretty
quick for a 6502, which gets a lot of milage out of a given clock cycle much
like RISC processors.  The 'obvious' speed increase, 100% (a jump to 3.5+ Mhz)
requires a 4 Mhz rated 6502. This is now available. Initially from Western 
Design in the form of the 65C02.

But is it a 6502?

The Atari XL & XE, however, don't use a 6502.  They use a custom version of
the 6502.  Because on the Atari the 6502 processor has to share memory with
Antic, (which accesses memory on its own to update the screen,) it has to be
able to come 'off the bus,' or 'tri-state,' while Antic does its job.  On the
original 400/800 design, a series of tri-state buffers surround the 6502 and 
do the job of 'detaching' the 6502.  To lower the chip count on the XL & XE 
lines, Atari developed a custom version of the 6502 which had the simple 
tri-state buffers built-in.  Thus, any processor upgrade for the XL/XE lines
would have to replace these buffers since the only high speed 6502s are 
real 6502s and not Atari's custom version.  My guess is the Turbo/816 mod
has these buffers on it.

Memory chips

Many Atari's are still using original RAM chips which are too slow to handle
the CPU's requests at higher speeds.  Fortunately, memory upgrades are based
on 256K DRAM's and they're almost always fast enough.  Now, higher speeds are
trivial.

ROMs

The Atari ROMs weren't particularly slow, but may, depending on the speed-up
attempted, need to be replaced with faster current technology EPROMs.

What to speed up?

The Atari custom chipset is, necessarily, old.  Those chips aren't likely 
to survive any speed-up attempt.  Further, the 1.7+ Mhz clock rate of the
Atari is tied to the NTSC Television rate.  Antic & GTIA need that rate in
order to work with the television set.  Our design opted to simply speed 
up the 6502 and let the rest of the system continue to operate as before.

What about games?
 
My theory is games should work OK. Most games timed themselves off of VBLANK
or the timer, which are external to the 6502 clock rate.

How can you speed up just the CPU?

Surprisingly to most people, in the Atari the 6502 doesn't run the show. 
Antic does.  Antic, when it needs access to memory, just reaches over and
shuts down the 6502.  Thus, Antic could care less what speed the 6502 runs
when it's not involved.

6502 vs 65C02 timings
 
Now some real problems: the Western Design 65C02 was the first available
6502 that could actually handle 4 Mhz.  However, beyond the relatively
simple missing buffers, Ken pointed out a fundamental difference: The 65C02
is _edge_ triggered, the 6502 is _level_ triggered. That is, the 6502
considers an 'on' signal to be when the level reaches 5 volts, where the 
65C02 considers 'on' to be when the voltage changes.
 
This is bad. Antic sends a 'halt' signal which shuts down the 6502 while
it accesses memory. This signal hits in time for the 6502, but a Western
Design chip sees the signal level come up _after_ it's started into it's
next cycle.  It may arrive in time in a normal speed environment, but at
double speed, the 65C02 will be already chugging along and not stop in time.

An alternate halt signal

The next thought was then "what about an earlier halt signal?"  Ken stared
at the schematics and found that, by combining some signals 'upstream' of 
Antic, we could re-create the halt signal.  We then attached a dual-trace 
scope to the 6502 halt line and the critical signal, and found that the 
new signal in fact does hit before Antic's halt. Approximately 10 ns in 
advance.

Unfortunately, this signal alone is not enough. The combination of it and
one or two other signals is needed to recreate 'halt'.  A circuit to decode
this signal involves three levels of logic.  Given our extremely tight 
10 ns window (est. from a scope display) we figured that using 74 S-series
logic, which has a nominal gate delay of 3 ns, it would just fit.  At this
point, life kicked in and we did not build a prototype to test it out.
My apologies for not having more specific information - this is from memory
of work done 4 or 5 years ago.

Post-mortem considerations

Since we embarked on this effort, a couple of new things have come along.
First off, we now have new logic devices available, including the 74HCT family,
which is supposedly pretty quick.  Another option are the now widely available
high speed programmable gate arrays and other field programmable logic, which
may or may not be fast enough.
 
Also, in the years inbetween 6502's have progressed.  At one point, I saw a 
reference to a real Rockwell 6502 rated at 4 Mhz.  This, should it be a high
speed version of the original design, would eliminate much of the hoop-jumping
involved with Western Design's chips.  'Sally's' tri-state buffers would of
course still need to be replicated.

This is exactly the kind of project that, given this info, would be trivial 
for a hardware designer.  Perhaps you know one? For anyone interested in this
project, I will coordinate efforts on The Club's ATARI conference.  An
extensive library of memory-upgrade docs, software and testing tools is also
available on The Club II.

All in all, this is an interesting project because the solution involves 
technology released as much as 15 years after the 8-bit's original design.
Realistically, with today's technology one could reasonably implement an
entire Atari-8-bit-compatible motherboard on a single field-programmable gate
array, let alone ASIC; transistor counts in 1978 were nothing.  It is a 
fitting tribute to the 8-bit's clean design that it could continue to thrive
well into a time where it could fit in a wristwatch.

Terry Conklin
conklin@theclub.mi.org            The Club (517) 372-3131
(517) 484-2824 voice              Club II  (313) 334-8877

Copyright 1993 Terence Conklin.  Anyone interested in reprinting this just
give me a ring. 
-- 
         Michael Current, Cleveland Free-Net 8-bit Atari SIGOp
Carleton College, Northfield, MN, USA / UUCP: ...!umn-cs!ccnfld!currentm
      Internet: currentm@carleton.edu / Cleveland Free-Net: aa700





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